//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================
#ifndef _BL_CONFIG_H_
#define _BL_CONFIG_H_

/* CPU */
#define USE_BULVERDE

#define P1_BOARD

#include "bulverde.h"

/* Target board */
#define OMEGA

#define TARGET_MACHINE "OMEGA"
#define VERSION "v1.0usb"

/* default kernel boot argument */
#define BOOT_ARG0 0
#define BOOT_ARG1 0


/****************************************************************
 *
 *         Flash Memory Map
 *
 ****************************************************************/
#define KERNEL_RAM_START		0xA0020000//0xA0208000

#define BL_FLASH_START			0x00000000
#define BL_FLASH_LENGTH			0x00020000

#define TAT_FLASH_START			0x00020000
#define TAT_FLASH_LENGTH		0x00020000

#define KERNEL_FLASH_START		0x00040000
#define KERNEL_FLASH_LENGTH		0x00100000

#define ROOT_FLASH_START		0x00140000
#define ROOT_FLASH_LENGTH		0x00380000

#define USER_FLASH_START		0x004C0000
#define USER_FLASH_LENGTH		0x01800000

#define USERDATA_FLASH_START	0x01CC0000
#define USERDATA_FLASH_LENGTH	0x00220000

#define PTABLE_FLASH_START		0x01EE0000
#define PTABLE_FLASH_LENGTH		0x00020000

#define INITIMAGE_FLASH_START	0x01F00000
#define INITIMAGE_FLASH_LENGTH	0x00100000

#define DOC_PAGES_IN_BLOCK     (128)
#define DOC_PAGE_SIZE          (512)
#define DOC_BLOCK_SIZE         (DOC_PAGE_SIZE*DOC_PAGES_IN_BLOCK)

/* Size of FLASH storage */
//#define DOC_SIZE_128M

#ifdef DOC_SIZE_128M

#define BDK_NUMBER      2
#define BDTL_NUMBER     4

#define SIZE_128M                0x08000000L             /*128M*/

#define BDK0_LENGTH             (1024 * 1 * 1024L)       /*blob (1024*2*1024) contain sub partition for logo tat tattable */
#define BDK1_LENGTH             (1024 * 2 * 1024L)       /*kernel 2M*/
#define BDTL0_LENGTH            (1024 * 42 * 1024L)      /*rootfs 42M*/
#define BDTL1_LENGTH            (1024 *23 * 1024L)
#define BDTL2_LENGTH            (1024 * 5 * 1024L)
#define BDTL3_LENGTH            (SIZE_128M - BDK0_LENGTH - BDK1_LENGTH - BDTL0_LENGTH - BDTL1_LENGTH - BDTL2_LENGTH) /*qtopia*/

#else //DOC_SIZE_128M
#define BDK_NUMBER      2
#define BDTL_NUMBER     2

#define SIZE_64M                0x04000000L             /*64M*/

#define BDK0_LENGTH             (1024 * 1 * 1024L)       /*blob (1024*2*1024) contain sub partition for logo tat tattable */
#define BDK1_LENGTH             (1024 * 5 * 1024L)       /*kernel 5M*/
#define BDTL0_LENGTH            (1024 * 32 * 1024L)       /*smartphone app 28M and database log 4M*/
#define BDTL1_LENGTH            (SIZE_64M - BDK0_LENGTH - BDK1_LENGTH - BDTL0_LENGTH) /*user data*/

#endif //DOC_SIZE_128M

#define LOGO_SUBPARTITION       (4*DOC_BLOCK_SIZE)


/* memory address */
#define RAM_START				0xA0000000
#define RAM_BOOT_LOADER_AREA_START_OFFSET_FROM_RAM_START 0x03C00000
#define RAM_BOOT_LOADER_AREA_LENGTH  0x00100000
#define RAM_STACK_END_OFFSET_FROM_RAM_START 0x03FFFFFC


/******************************************************************/
/*      Peripheral settings                                       */
/******************************************************************/
/* default serial port */
#define ENABLE_STUART
//#define ENABLE_FFUART
//#define ENABLE_BTUART

#define CONFIG_USBSERIAL_SUPPORT

/* serial port */
#define TERMINAL_SPEED baud_115200

/* internal timer resolution */
#define TIMER_TICK_PER_SEC 100 /* timer interrupt per sec. */


/*******************************************************************************/
/*     MAINSTONE Memory Controller Value                                       */
/*******************************************************************************/

/*
 * SDRAM Settings
 */
#define MDCNFG_VAL	0x0AC9 //SDRAM Config Reg (CL=3, Normal Addressing, 4 Banks, 13 row bits, 9 col bits, 32-bit port width)
//#define MDCNFG_VAL	0x000009C9 //SDRAM Config Reg (*CL=2, Normal Addressing, 4 Banks, 13 row bits, 9 col bits, 32-bit port width) This is fine for SDCLK=65MHz, and is really close for SDCLK=100MHz

#define MDREFR_VAL	0x000BA01E //SDRAM Refresh Reg (SDCLK[0]=MemClk/4, APD, SDCLK[1]=MemClk/2, DRI=x01E (7.62us refreshes)) POST value --> 0x0003801E

#define MDMRS_VAL	0x00000000 //SDRAM Mode Reg Set Config Reg (MDMRS1: burst reads & writes)
#define MDMRSLP_VAL	0x0000C008 //SDRAM Mode Reg Set Config Reg - Low Power (enabled, 45 C TCR, all banks PASR (partial array self refresh))


/*
 * Static Memory Settings
 */
#define K3_MSC0_VAL	0x27A8 //Static Mem. Control Reg 0 (nCS0,1)=(Boot Flash, Secondary Flash)
#define L3_MSC0_VAL	0xA7AB39FA //just reversed K3's - Borrowing J3's for ASync. Tyax at the moment

//#define MSC0_VAL	0x39F2CEA3 //RDN 7-->4  R: no dicey, 2)doubled RDN and RRR R: no dicey
//#define MSC0_VAL	0x39F297E3 //RDN 7-->4  R: no dicey, 2)doubled RDN and RRR R: no dicey, all F's R: better, but copy fails, FFA3 (no RDF adjustment) R:bad, A7C3 (only RDF adjusted) R: yeah!

//#define MSC1_VAL	0x0000A691 //Static Mem. Control Reg 1 (enable nCS2 for DOC)
#define MSC1_VAL	0x0000FFF8 //Static Mem. Control Reg 1 (enable nCS2 for DOC)

#define MSC2_VAL	0x00000000 //Static Mem. Control Reg 2 (disable nCS4,5)


/*
 * PCMCIA and CF Interfaces
 */
#define	MECR_VAL	0x00000001 //Expansion memory (PCMCIA/CF) Bus Config (NOS=2, card is NOT there)
#define	MCMEM0_VAL	0x0001C391 //Card I-face Common Mem Space socket 0 timing config
#define	MCMEM1_VAL	0x0001C391 //Card I-face Common Mem Space socket 1 timing config
#define	MCATT0_VAL	0x0001C391 //Card I-face Attribute Space socket 0 timing config
#define	MCATT1_VAL	0x0001C391 //Card I-face Attribute Space socket 1 timing config
#define	MCIO0_VAL	0x0001C391 //Card I-face I/O Space socket 0 timing config
#define	MCIO1_VAL	0x0001C391 //Card I-face I/O Space socket 1 timing config


/*
 * Synch. Static Memory: Processor Daughter Card's K18 FLASH is capable of operating synchronously.
 */
#define SXCNFG_VAL	0x40044004 //Synch. Static Mem. Config. Reg. (Burst-of-8 reads, CL=4, SDCLK return latching)


/*
 * Alternate Bus Masters - Fly-By-DMA Mode (unused on Mainstone)
 */
#define FLYCNFG_VAL	0x00000000 //Fly-by-DMA config. reg (==POR: both DVALs active low)

/*******************************************************************************/
/*     MAINSTONE GPIO values						       */
/*******************************************************************************/
#ifdef P1_BOARD // P1 Board settings
#define GPDR0_VAL	0xD0FF901B
#define GPDR1_VAL	0xFFFFABB3
#define GPDR2_VAL	0x1FE3FFFF
#define GPDR3_VAL	0x0003038D

#define GRER0_VAL	0x00000000
#define GRER1_VAL	0x00000000
#define GRER2_VAL	0x00000000
#define GRER3_VAL	0x00000000
#define GFER0_VAL	0x00000000
#define GFER1_VAL	0x00000000
#define GFER2_VAL	0x00000000
#define GFER3_VAL	0x00000000

#define	GPSR0_VAL	0x00008800
#define GPSR1_VAL	0x03CF0002
#define GPSR2_VAL	0x21FC0000
#define GPSR3_VAL	0x00000000

#define GPCR0_VAL	0x00000000
#define GPCR1_VAL	0x00000000
#define GPCR2_VAL	0x00000000
#define GPCR3_VAL	0x00000000

#define GAFR0_L_VAL	0x02800000
#define GAFR0_U_VAL	0x59E5404A
#define GAFR1_L_VAL     0x999AA052
#define GAFR1_U_VAL	0xAAA00000
#define GAFR2_L_VAL	0x0AAAAAAA
#define GAFR2_U_VAL	0xA90F0154
#define GAFR3_L_VAL	0x555A950C
#define GAFR3_U_VAL	0x00001595
#endif

#ifdef P2_BOARD // P2 Board settings
#define GPDR0_VAL	0xCF056000
#define GPDR1_VAL	0xFF20A9D7 // TODO: should be 0xFF22A9D7, for GPIO49 out
#define GPDR2_VAL	0x06C57FFF
#define GPDR3_VAL	0x01EB1381

#define GRER0_VAL	0x00000000
#define GRER1_VAL	0x00000000
#define GRER2_VAL	0x00000000
#define GRER3_VAL	0x00000000
#define GFER0_VAL	0x00000000
#define GFER1_VAL	0x00000000
#define GFER2_VAL	0x00000000
#define GFER3_VAL	0x00000000

#define	GPSR0_VAL	0x00000000
#define GPSR1_VAL	0x00000000
#define GPSR2_VAL	0x00000000
#define GPSR3_VAL	0x00000000

#define GPCR0_VAL	0x00000000
#define GPCR1_VAL	0x00000000
#define GPCR2_VAL	0x00000000
#define GPCR3_VAL	0x01000000

#define GAFR0_L_VAL	0x26000000
#define GAFR0_U_VAL	0xA5000088 // TODO: should be 0xA5000288, for GPIO20 nDMARQ
#define GAFR1_L_VAL 0x69980282
#define GAFR1_U_VAL	0xAAA07851 // TODO: should be 0xAAA07859, for GPIO49 nIRQ
#define GAFR2_L_VAL	0x22AAAAAA
#define GAFR2_U_VAL	0x0104AFC8
#define GAFR3_L_VAL	0x565A95FF
#define GAFR3_U_VAL	0x00001409
#endif



#endif // _BL_CONFIG_H_
